Semiconductor device

ABSTRACT

A semiconductor device is disclosed. One embodiment provides a device including a carrier, an electrically insulating layer arranged over the carrier and a first semiconductor chip arranged over the electrically insulating layer, wherein the first semiconductor chip has a first contact element on a first surface and a second contact element on a second surface.

BACKGROUND

This invention relates to a semiconductor device and a fabricationmethod thereof.

Power semiconductor chips may, for example, be integrated intosemiconductor devices. Power semiconductor chips are suitable inparticular for the switching or control of currents and/or voltages.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of embodiments and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments andtogether with the description serve to explain principles ofembodiments. Other embodiments and many of the intended advantages ofembodiments will be readily appreciated as they become better understoodby reference to the following detailed description. The elements of thedrawings are not necessarily to scale relative to each other. Likereference numerals designate corresponding similar parts.

FIG. 1 schematically illustrates a cross section of a device 100 as anexemplary embodiment.

FIG. 2 a schematically illustrates a cross section of a device 200 as afurther exemplary embodiment.

FIG. 2 b schematically illustrates a top plan view of the device 200.

FIGS. 3 a to 3 f schematically illustrate an exemplary embodiment of amethod to fabricate the device 200.

DETAILED DESCRIPTION

In the following Detailed Description, reference is made to theaccompanying drawings, which form a part hereof, and in which is shownby way of illustration specific embodiments in which the invention maybe practiced. In this regard, directional terminology, such as “top,”“bottom,” “front,” “back,” “leading,” “trailing,” etc., is used withreference to the orientation of the Figure(s) being described. Becausecomponents of embodiments can be positioned in a number of differentorientations, the directional terminology is used for purposes ofillustration and is in no way limiting. It is to be understood thatother embodiments may be utilized and structural or logical changes maybe made without departing from the scope of the present invention.

It is to be understood that the features of the various exemplaryembodiments described herein may be combined with each other, unlessspecifically noted otherwise.

In the following, embodiments are described with reference to thedrawings, wherein like reference numerals are generally utilized torefer to like elements throughout, and wherein the various structuresare not necessarily drawn to scale. In the following description, forpurposes of explanation, numerous specific details are set forth inorder to provide a thorough understanding of one or more aspects ofembodiments. It may be evident, however, to a person skilled in the artthat one or more aspects of the embodiments may be practiced with alesser degree of these specific details. In other instances, knownstructures and devices are illustrated in block diagram form in order tofacilitate describing one or more aspects of the embodiments. Thefollowing description is therefore not to be taken in a limiting sense,and the scope of the application is defined by the appended claims.

Devices with a semiconductor chip arranged over a carrier are describedbelow. The carrier may be of any shape, size or material. During thefabrication of the device the carrier may be provided in a way thatother carriers are arranged in the vicinity and are connected byconnection means to the carrier with the purpose of separating thecarriers. The carrier may be fabricated from metals or metal alloys, inparticular copper, copper alloys, aluminum, aluminum alloys, or othermaterials. It may further be electrically conductive and may serve,inter alia, as a heat sink for dissipating the heat generated by thesemiconductor chip. For example, the carrier may be a lead-frameconsisting of one or more die pads and pins.

Semiconductor chips as described below may be of extremely differenttypes and may include for example integrated electrical orelectro-optical circuits. The semiconductor chips may be, for example,configured as power transistors, power diodes, control circuits,microprocessors or microelectromechanical components. In particular,semiconductor chips having a vertical structure may be involved, that isto say that the semiconductor chips may be fabricated in such a way thatelectric currents can flow in a direction perpendicular to the mainsurfaces of the semiconductor chips. A semiconductor chip having avertical structure may have contact elements in particular on its twomain surfaces, that is to say on its top side and bottom side. Inparticular, power transistors and power diodes may have a verticalstructure. By way of example, the source terminal and gate terminal of apower transistor and the anode terminal of a power diode may be situatedon one main surface, while the drain terminal of the power transistorand the cathode terminal of the power diode are arranged on the othermain surface. A power diode may be embodied in particular as a Schottkydiode. Furthermore, the devices described below may include integratedcircuits to control the integrated circuits of other semiconductorchips, for example, the integrated circuits of power transistors orpower diodes. The semiconductor chips need not be manufactured fromspecific semiconductor material and, furthermore, may contain inorganicand/or organic materials that are not semiconductors, such as forexample insulators, plastics or metals. Moreover, the semiconductorchips may be packaged or unpackaged.

The described semiconductor chips have contact elements which allowelectrical contact to be made with the semiconductor chips. The contactelements may be composed of any desired electrically conductivematerial, for example of a metal, such as aluminum, gold or copper, ametal alloy or an electrically conductive organic material. Thesemiconductor chips have at least one first contact element on a firstsurface and at least one second contact element on a second surface. Thecontact elements may be situated on one or more active surfaces of thesemiconductor chips or on other surfaces of the semiconductor chips.

In the case of the device including more than one semiconductor chip,the semiconductor chips may be in a functional relationship to eachother. For example, one of the semiconductor chips may control anotherone of the semiconductor chips.

The devices described below further contain an electrically insulatinglayer arranged over the carrier. The electrically insulating layer mayconsist of any material, for example it may contain metal oxides (inparticular aluminum oxide, silver oxide, titanium oxide, copper oxide,chromium oxide or zinc oxide), semiconductor oxide (in particularsilicon oxide), epoxy resin, diamond-like carbon, imides, organicmaterials, ceramic materials, glasses or polymers, such as parylene. Ifthe electrically insulating layer is fabricated from silicon oxide, itmay further contain other elements, such as phosphorus or boron.

The thickness of the electrically insulating layer may, for example, bein the range between 10 nm and 150 μm, in particular it may be in therange between 1 μm and 50 μm and more particular it may be in the rangebetween 1 μm and 10 μm. The electrically insulating layer may bethermally conductive. The thermal conductivity of the electricallyinsulating layer may, for example, be in the range between 0.01 W/mK and500 W/mK, in particular in the range between 0.1 W/mK and 50 W/mK. Theelectrically insulating layer may have a high blocking capability toprovide a good electrical insulation. The values for the blockingcapability may, for example, be in the range between 1 V/μm and 1000V/μm, in particular in the range between 10 V/μm and 200 V/μm and moreparticular in the range between 100 V/μm and 200 V/μm.

The electrically insulating layer may cover any fraction of any numberof surfaces of the carrier and may additionally cover any othercomponent of the device to any degree, in particular the semiconductorchips and the contact elements of the semiconductor chips.

The electrically insulating layer may be fabricated by any meansappropriate to fabricate an electrically insulating layer. For example,planar techniques may be employed to fabricate the electricallyinsulating layer. The term “electrically insulating” refers to theproperty of the layer to be at most only marginally electricallyconductive relatively to other components of the device. In particular,the term “electrically insulating” refers to the at most only marginalelectrical conductivity in a direction mainly perpendicular to the planeof extension of the electrically insulating layer.

The electrically insulating layer may have adhesive properties withrespect to the carrier and also to possible molding materials applied tothe device with the purpose of packaging the part of the carrier wheresemiconductor chips are placed. The adhesiveness of the electricallyinsulating layer with respect to molding materials and/or the carriermay vary according to the material of the molding materials and/or thecarrier.

During the fabrication of the device, parts of the electricallyinsulating layer may be removed in order to be able to establishelectrical connections between components of the device. For example,prior to applying the electrically insulating layer to the carrier,contact elements or parts of the semiconductor chips may be covered by amasking layer to prevent the electrically insulating layer to bedeposited on the areas covered by the masking layer. After thedeposition of the electrically insulating layer, the masking layer islifted off. Furthermore, when using a galvanic method to deposit theelectrically insulating layer, an appropriate electrical potential maybe applied to the contact elements of the semiconductor chip to preventthe contact elements to be covered with the electrically insulatinglayer. Further methods used during the deposition process are e.g.,etching or sputtering methods.

A further example of an implementation of the electrically insulatinglayer is an electrically insulating foil, which is laminated on thecarrier and structured. The structuring of such an electricallyinsulating foil may for example be achieved by a stamping process, laserablation or any suitable process known to a person skilled in the art.In the case of the carrier being implemented as a lead-frame including adie pad and pins, the electrically insulating foil may bridge gapsbetween the die pad and the pins. The electrically insulating foil mayact as a platform for the deposition of further layers.

The devices described below may further include an electricallyconductive layer arranged between the electrically insulating layer andat least one of the semiconductor chips. The electrically conductivelayer may be fabricated by any means appropriate to fabricateelectrically conductive layers. Exemplary fabrication methods aregalvanic or chemical deposition processes. In principle, the fabricationprocesses for the electrically conductive layer may be of similar typeas the above-mentioned fabrication processes for the fabrication of theelectrically insulating layer (e.g., masking, etching, etc.).

Regarding its geometric form or material composition, the electricallyconductive layer may be fabricated arbitrarily. The electricallyconductive layer may for example be embodied as a plurality of longishstructures or an area-wide coating. Any conductive material may beemployed for its fabrication, like for example metals (copper, aluminum,gold, etc.), metal alloys or organic conductors. Generally, theelectrically conductive layer does not need to be fabricatedhomogeneously or only from one specific material, i.e. variouscompositions and concentrations of the materials contained in theelectrically conductive layer are possible.

The electrically conductive layer may provide electrical connectionsbetween different components of the device. In the case of the carrierbeing embodied as a lead-frame including a die pad and pins, theelectrically conductive layer may in particular provide an electricalcoupling between the semiconductor chips and the pins of the lead-frame.

It is to be noted that the number of electrically insulating and/orelectrically conductive layers used to fabricate the device mayrespectively not be limited to one or two. As a matter of fact, anynumber of layers stacked on top of each other may be provided. Multipleelectrically insulating layers may be stacked on top of each other, butmay also be separated by one or more electrically conductive layers.Each of the multiple electrically insulating layers and/or theelectrically conductive layers may respectively have a differentthickness, material composition and degree of carrier-covering than theremaining number of electrically insulating layers and/or electricallyconductive layers used to fabricate the device.

The devices described herein may further include a molding compound orpackage covering parts of the device. The molding compound may, forexample, be made of a thermoplastic resin or a thermosetting plastic,for example epoxy resin. For example, at least one surface of thecarrier may not completely be covered with the molding compound. In thismanner, a coupling of the carrier to a heat sink may provided. The heatsink may be manufactured of a material with a high thermal conductivity(for instance a metal or a metal alloy) to support the heat transportaway from the device. Furthermore, the device may be mounted onto acircuit board, with the surface of the carrier which is not covered withthe molding compound facing the circuit board.

FIG. 1 schematically illustrates a device 100 in a cross section as anexemplary embodiment. The device 100 includes a carrier 1, anelectrically insulating layer 2 arranged over the carrier 1 and a firstsemiconductor chip 3 arranged over the electrically insulating layer 2.The first semiconductor chip 3 illustrates a first contact element 4 aon its upper surface and a second contact element 4 b on its bottomsurface that faces the carrier 1. It is understood that the firstsemiconductor chip 3 may include further contact elements depending onits desired functionality.

The device 100 may further include an electrically conductive layer 5arranged between the electrically insulating layer 2 and the firstsemiconductor chip 3. The electrically conductive layer 5 may be incontact with the second contact element 4 b thereby providing thepossibility of an electrical connection between the first semiconductorchip 3 and further electrical components (not illustrated). It is to benoted that the electrically insulating layer 2 may electrically isolatethe carrier 1 from the first semiconductor chip 3 and/or theelectrically conductive layer 5. Furthermore, the electricallyinsulating layer 2 may be thermally conductive. In this case, theelectrically insulating layer 2 may conduct the heat generated by thefirst semiconductor chip 3 to the carrier 1.

FIG. 2 a schematically illustrates a device 200 in a cross section as afurther exemplary embodiment. The device 200 includes a carrier element,which in this case is embodied as a lead-frame consisting of a die pad 1a and pins 1 b and 1 c. Due to the chosen perspective of FIG. 2 a, thepins 1 b and 1 c hide further pins arranged behind them. It is wellknown to a person skilled in the art that the number of pins of alead-frame may be arbitrary and generally depends on the overallfunctionality of the device 200. It is to be noted that FIG. 2 a is bestviewed in combination with FIG. 2 b that illustrates the top plan viewof the device 200.

The device 200 further includes an electrically insulating layer 2arranged over the die pad 1 a and the pins 1 b and 1 c. As alreadymentioned in preceding paragraphs, the electrically insulating layer 2may be made of any materials, fabricated in various ways and be ofarbitrary geometrical form depending on the desired functionality of thedevice 200. For example, the electrically insulating layer 2 may bedeposited by planar techniques. In FIG. 2 a, the electrically insulatinglayer 2 bridges the gaps between the die pad 1 a and the depicted pins 1b and 1 c, respectively. In this manner, it becomes possible to depositfurther layers over the electrically insulating layer 2 even in theregion of the gaps. Naturally, the device 200 may further include pinsthat are not connected to the die pad 1 a by using the electricallyinsulating layer 2. It is to be noted that the electrically insulatinglayer 2 is opened (or alternatively not deposited) at certain areas toprovide the possibility to electrically connect the underlying layers orcomponents.

The device 200 further includes a second semiconductor chip 6, which mayhave the function of controlling the first semiconductor chip 3. Thecontrol chip 6 may be applied onto the die pad 1 a by arbitrarytechniques well know in the art. For example, the control chip 6 may beattached to the die pad 1 a via a soldering process, likesoft-soldering, hard-soldering or diffusion-soldering. Anotherpossibility to attach the control chip 6 to the die pad 1 a may be theemployment of an adhesive layer, which may be electrically conductive orinsulating. In the case of the device 200, the control chip 6 is indirect contact with the die pad 1 a. It would, however, also be possibleto attach the control chip 6 on the electrically insulating layer 2, aslong as the functionality of the device 200 is not undesirably changed.Consequently, the processes of attaching the control chip 6 anddepositing the electrically insulating layer 2 are interchangeable.

The device 200 further includes an electrically conductive layer 5deposited over the electrically insulating layer 2, the pins 1 b and 1 cand parts of the control chip 6. Similar to the electrically insulatinglayer 2 beneath it, the electrically conductive layer 5 may be made ofany materials, deposited in various ways and be of arbitrary geometricalform depending on the desired functionality of the device 200. Theelectrically conductive layer 5 may establish electrical connectionsbetween the pins 1 b and 1 c and further components of the device 200,such as the semiconductor chips 3 and 6. In the case of the pin 1 c, anelectrical connection to the control chip 6 has been implemented byusing the electrically conductive layer 5. The pin 1 c may be connectedto external devices on its bottom side (or generally on positions thatare not covered by other components of the device, like e.g., a moldingcompound). The electrically conductive layer 5 deposited on the controlchip 6 may also be used to attach other electrically conductiveelements, such as bond wires (cf. the attached bond wire 7 a on the topside of the control chip 6).

In the present embodiment, the first semiconductor chip 3 is implementedas a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 3.On the top surface of the power MOSFET 3, two contact elements 4 a′ and4 a″ are arranged with the contact element 4 a′ representing a sourceterminal and the contact element 4 a″ representing a gate terminal. Acontact element 4 b representing a drain terminal is arranged on thebottom surface of the power MOSFET 3. The arrangement of the contactelements 4 a′, 4 a″ and 4 b leads to an electric current flowing in adirection perpendicular to the main surfaces of the power MOSFET 3. Thepower MOSFET 3 is applied onto the electrically conductive layer 5 byusing, for example, a soldering process (e.g., soft-soldering,hard-soldering, diffusion-soldering), but may also be attached to theelectrically conductive layer 5 via an adhesive layer.

The contact element 4 a″ (i.e. the gate terminal) on the top surface ofthe power MOSFET 3 is electrically coupled to the control chip 6 by abond wire 7 a. Naturally, this electrical connection could also beestablished by an electrically conductive layer or a clip. The twosemiconductor chips 3 and 6 are functionally coupled to each other, withthe control chip 6 controlling the power MOSFET 3. The contact element 4a′ (i.e. the source terminal) on the top surface of the power MOSFET 3is electrically coupled to one or more of the pins 1 d of thelead-frame. The pins 1 d cannot be seen from FIG. 2 a due to theirarrangement behind the pins 1 b. The connection is established by a bondwire 7 b (not completely apparent), but may also be realized by anelectrically conductive layer or a clip. The pins 1 d may be connectedto external devices via their bottom surfaces. The contact element 4 b(i.e. the drain terminal) on the bottom surface of the power MOSFET 3 iselectrically coupled to the pin 1 b by the electrically conductive layer5. As illustrated in FIG. 2 b, the electrically conductive layer 5 mayalso provide a connection to multiple drain pins 1 b. The drain pins 1 bmay be connected to external devices via their bottom surfaces.

It is to be noted that due to the arrangement of the electricallyinsulating layer 2 and the electrically conductive layer 5, the powerMOSFET 3 and in particular its drain terminal 4 b are electricallyinsulated from the control chip 6 and the die pad 1 a. The drain voltageof a power MOSFET can be up to 1 kV or more. Since the die pad 1 a iselectrically insulated from the power MOSFET 3 (i.e. they do not havethe same electrical potential), the control chip 6 may contact the diepad 1 a without experiencing any damage caused by the high voltages ofthe power MOSFET 3.

Components of the device 200 may be covered with a molding compound 8.The molding compound 8 may be implemented according to precedingparagraphs and usually serves to protect components of the device 200against environmental influences like dirt, humidity or mechanicalimpact. In FIGS. 2 a and 2 b, the molding compound 8 does not cover therespective bottom sides of the pins 1 b, 1 c and 1 d, as well as thebottom side of the die pad 1 a.

A heat sink, which is not illustrated in FIG. 2 a, may be thermallycoupled to the die pad 1 a. During operation, the heat generated by thepower MOSFET 3 and the control chip 6 may be dissipated away from thedevice 200 by the heat sink. An effective dissipation path proceeds fromthe bottom surfaces of semiconductor chips 3 and 6 towards the heatsink, thereby crossing the layers 2 and 5 and the die pad 1 a. Thethickness and the material of the electrically insulating layer 2 shouldthus be chosen in a way to provide both, a high thermal conductivity andgood insulating properties at the same time. The bottom surface of thedevice 200 may also be used to mount the device 200 on a circuit board,for example a PCB (Printed Circuit Board). The parts of the die pad 1 aand the pins 1 b to 1 d, which are not covered with the molding compound8 can be soldered to contact areas of the circuit board.

FIG. 2 b schematically illustrates a top plan view of the device 200with the context between FIGS. 2 a and 2 b being self-explanatory to aperson skilled in the art. The molding compound 8 encapsulates most ofthe components of the device 200 and is simply indicated by a dashedline. Due to the chosen perspective and for the sake of clarity theelectrically insulating layer 2 is not explicitly illustrated. Itbecomes apparent from FIG. 2 b that the lead-frame includes multipledrain pins 1 b, multiple pins 1 c contacting the control chip 6 andmultiple source pins 1 d. It is to be noted that FIG. 2 b explicitlyillustrates the connection between the source pins 1 d and the powerMOSFET 3 by using the bond wires 7 b, which are not completely apparentin FIG. 2 a.

In FIGS. 3 a to 3 f different stages of the fabrication of the device200 are exemplarily illustrated. In order to manufacture the device 200,first the lead-frame including the die pad 1 a and the pins 1 b to 1 dare provided (see FIG. 3 a). The lead-frame may be fabricated from ametal, such as copper, iron, nickel or aluminum, or a metal alloy oranother electrically conductive material. The control chip 6 is thenmounted onto the die pad 1 a (see FIG. 3 b).

An electrically insulating foil 2 is deposited on top of the die pad 1 aand the pins 1 b and 1 c to bridge the gaps between them (see FIG. 3 c).The electrically insulating foil 2 may, for example, be laminated ontothe lead-frame and may be structured by a stamping process, laserablation or any other suitable process known to a person skilled in theart. The electrically insulating foil 2 may be manufactured from aplastic or synthetic material or any other suitable material.

The electrically insulating foil 2 may act as a platform for thedeposition of further layers, such as the electrically conductive layer5 (see FIG. 3 d). The electrically conductive layer 5 may be depositedusing any appropriate deposition method, such as electroless or galvanicplating processes, physical vapor deposition, chemical vapor deposition,sputtering, spin-on processes, spray depositing or ink jet printing.Copper, iron, nickel or other metals or metal alloys may be used asmaterials for the electrically conductive layer 5.

The power MOSFET 3 may be placed on the electrically conductive layer 5with its drain terminal 4 b facing the die pad 1 a (see FIG. 3 e). Theelectrical connection between the drain terminal 4 b and theelectrically conductive layer 5 may, for example, be produced by reflowsoldering, vacuum soldering, diffusion soldering or adhesive bonding byusing a electrically conductive adhesive.

If diffusion soldering is used as a connecting technique, it is possibleto use solder materials which lead to intermetallic phases after the endof the soldering operation at the interface between the drain terminal 4b and the electrically conductive layer 5 on account of interfacediffusion processes. In this case, the use of AuSn, AgSn, CuSn, AgIn,AuIn or CuIn solders is conceivable. If the power MOSFET 3 is adhesivelybonded to the electrically conductive layer 5, it is possible to useconductive adhesives which may be based on epoxy resins and be enrichedwith gold, silver, nickel or copper in order to produce the electricalconductivity.

Other electrical connections with the terminals 4 a′ and 4 a″ on the topsurface of the power MOSFET 3 may be established by the bond wires 7 aand 7 b as illustrated in FIG. 3 e.

The molding compound 8 is used to encapsulate the device 200 (see FIG. 3e). The molding compound 8 may encapsulate any portion of the device200, but leaves the bottom surfaces of the die pad 1 a and the pins 1 bto 1 d uncovered. Furthermore, as illustrated in FIG. 3 e the bottomsurfaces of the die pad 1 a and the pins 1 b to 1 d as well as a surfaceof the molding compound 8 may form a plane. The molding compound 8 maybe composed of any appropriate thermoplastic or thermosetting material,in particular it may be composed of material commonly used incontemporary semiconductor packaging technology. Various techniques maybe employed to cover the components of the device 200 with the moldingcompound 8, for example compression molding or injection molding.

In addition, while a particular feature or aspect of an embodiment mayhave been disclosed with respect to only one of several implementations,such feature or aspect may be combined with one or more other featuresor aspects of the other implementations as may be desired andadvantageous for any given or particular application. Furthermore, tothe extent that the terms “include”, “have”, “with”, or other variantsthereof are used in either the detailed description or the claims, suchterms are intended to be inclusive in a manner similar to the term“comprise”. The terms “coupled” and “connected”, along with derivativesmay have been used. It should be understood that these terms may havebeen used to indicate that two elements co-operate or interact with eachother regardless whether they are in direct physical or electricalcontact, or they are not in direct contact with each other. Furthermore,it should be understood that embodiments may be implemented in discretecircuits, partially integrated circuits or fully integrated circuits orprogramming means. Also, the term “exemplary” is merely meant as anexample, rather than the best or optimal. It is also to be appreciatedthat features and/or elements depicted herein are illustrated withparticular dimensions relative to one another for purposes of simplicityand ease of understanding, and that actual dimensions may differsubstantially from that illustrated herein.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat a variety of alternate and/or equivalent implementations may besubstituted for the specific embodiments illustrated and describedwithout departing from the scope of the present invention. Thisapplication is intended to cover any adaptations or variations of thespecific embodiments discussed herein. Therefore, it is intended thatthis invention be limited only by the claims and the equivalentsthereof.

1. A device, comprising: a carrier; an electrically insulating layerarranged over the carrier; a first semiconductor chip arranged over theelectrically insulating layer, wherein the first semiconductor chip hasa first contact element on a first surface and a second contact elementon a second surface: and a second semiconductor chip arranged over thecarrier.
 2. The device of claim 1, wherein the first semiconductor chipis a power semiconductor.
 3. The device of claim 1, wherein the carrieris electrically conductive.
 4. The device of claim 1, wherein thecarrier comprises a die pad and pins.
 5. The device of claim 4, whereinthe electrically insulating layer bridges at least one gap between thedie pad and at least one of the pins.
 6. The device of claim 1, whereinthe electrically insulating layer is an electrically insulating foil. 7.The device of claim 1, further comprising an electrically conductivelayer arranged between the electrically insulating layer and the firstsemiconductor chip.
 8. The device of claim 7, wherein the electricallyconductive layer electrically couples the first semiconductor chip to atleast one pin.
 9. (canceled)
 10. The device of claim 9, wherein thesecond semiconductor chip controls the first semiconductor chip.
 11. Thedevice of claim 9, wherein the second semiconductor chip is applied ontothe carrier.
 12. The device of claim 9, wherein the electricallyconductive layer extends to a surface of the second semiconductor chipfacing away from the carrier.
 13. The device of claim 1, furthercomprising a molding compound, wherein a surface of the carrier is onlypartially covered with the molding compound.
 14. The device of claim 1,wherein a heat sink is coupled to a surface of the carrier.
 15. Amethod, comprising: providing a carrier; depositing an electricallyinsulating layer over the carrier; and arranging a first semiconductorchip over the electrically insulating layer, wherein the firstsemiconductor chip has a first contact element on a first surface and asecond contact element on a second surface.
 16. The method of claim 15,wherein the carrier comprises a die pad and pins.
 17. The method ofclaim 15, further comprising depositing an electrically conductive layerover the electrically insulating layer before arranging the firstsemiconductor chip.
 18. The method of claim 17, wherein the electricallyconductive layer is deposited such that it electrically contacts atleast one of the pins.
 19. The method of claim 17, wherein the firstsemiconductor is arranged such that its first surface faces theelectrically conductive layer and the first contact element iselectrically connected to at least one of the pins by the electricallyconductive layer.
 20. The method of claim 15, further comprisingarranging a second semiconductor chip over the carrier before thedeposition of the electrically insulating layer.
 21. A device,comprising: a carrier comprising at least two parts separated by a gap;an electrically insulating layer arranged over the carrier and bridgingthe gap; and a semiconductor chip arranged over the electricallyinsulating layer.
 22. A device, comprising: a carrier; an electricallyinsulating layer arranged over the carrier; an electrically conductivelayer arranged over the electrically insulating layer; a semiconductorchip arranged over the electrically conductive layer, wherein a firstsurface of the semiconductor chip comprises a first contact element andfaces the electrically conductive layer: and a second semiconductor chiparranged over the carrier.
 23. A method, comprising: providing acarrier; laminating an electrically insulating foil onto the carrier;and arranging a first semiconductor chip over the electricallyinsulating foil, wherein the first semiconductor chip has a firstcontact element on a first surface and a second contact element on asecond surface.
 24. A device, comprising: a carrier, wherein the carriercomprises a die pad and pins; an electrically insulating layer arrangedover the carrier; and a first semiconductor chip arranged over theelectrically insulating layer, wherein the first semiconductor chip hasa first contact element on a first surface and a second contact elementon a second surface.
 25. A device, comprising: a carrier; anelectrically insulating layer arranged over the carrier, wherein theelectrically insulating layer is an electrically insulating foil; and afirst semiconductor chip arranged over the electrically insulatinglayer, wherein the first semiconductor chip has a first contact elementon a first surface and a second contact element on a second surface.